1. Field of the Invention
The present invention relates to a capacitor forming part of the electric circuit of a circuit board, a circuit board including such a capacitor, and methods of production of the same. The circuit board including a capacitor of the present invention forms a semiconductor module (semiconductor package) mounting a semiconductor chip.
2. Description of the Related Art
Semiconductor modules are being made increasingly denser in many applications. In accordance with this, when providing interconnect patterns in close proximity, it is important to prevent crosstalk noise between interconnects and fluctuations in potential of power lines etc. In particular, in the case of a semiconductor package mounting a high frequency semiconductor chip required for high speed switching operations, crosstalk noise occurs more easily along with a rise in the frequency. Further, high speed on/off operations of switching elements also cause switching noise. Due to this, the potential of the power lines etc. fluctuates more easily.
In the past, as means for eliminating such problems, a separate chip capacitor or other capacitor was mounted in a semiconductor package as a bypass capacitor for eliminating unnecessary coupling between circuits by signal lines or power lines (decoupling).
The method of the related art, however, suffered from the following problems. First, the degree of freedom of design of the interconnect patterns falls along with mounting of a separate chip capacitor etc.
Further, if the interconnect distance connecting a chip capacitor and semiconductor chip is long, the inductance becomes larger and the decoupling effect of the chip capacitor can no longer be obtained. Therefore, the chip capacitor etc. has to be mounted in as close proximity to the semiconductor chip as possible. The size of the chip capacitor etc., however, restricts the mounting position, so there were also limits to the proximity of arrangement with respect to the semiconductor chip.
Further, if mounting a chip capacitor or other capacitor in a semiconductor package, the package unavoidably becomes larger in size and heavier in weight. This runs counter to the current trend of the reduction of size and weight. In this regard as well, there were limits to measures through reduction of size of the chip capacitor etc.
The present assignee proposed a structure including a capacitor in a circuit board to solve the above problem of the related art in Japanese Patent Application No. 2001-57281. In this structure, the capacitor arranged between interconnect layers in the circuit board is comprised of a bottom electrode layer comprised of a valve metal, a dielectric layer comprised of an oxide of a valve metal, a solid electrolyte layer, and a top electrode layer stacked in that order.
The structure of the prior application eliminates the problem in the conventional structure mounting a chip capacitor separately on a circuit board by incorporating the capacitor in the circuit board, enables freedom of design of the interconnect patterns to be secured, greatly improves the degree of proximity between the capacitor and the semiconductor chip, and enables a reduction of the size and weight of the package.
The structure of the prior application, however, leaves room for further improvement in the production process, in particular the method of formation of the solid electrolyte layer. That is, in the process of production of the prior application, the solid electrolyte layer was formed by one of the following:
(1) formation by polypyrrole, a conductive polymer, by coating and thermal decomposition of a polymer,
(2) formation by a conductive polymer by electrolytic polymerization
(3) formation by stannous oxide or another conductive metal oxide by chemical vapor deposition (CVD) etc.
These methods of formation had room for improvement in the following respects: First, in the methods of formation of (1) and (2), polymers are formed using a liquid of a monomer solution, oxidizing agent, or electrolytic polymerization solution, so it is difficult to form the polymer in a predetermined shape at a predetermined position on the substrate.
Further, in the method of formation of (3), by using electrodeposition etc., the problem arising due to use of a liquid as explained above is solved, but the electroconductivity of a metal oxide is low, so obtaining a low ESR capacitor is difficult. The ESR, that is, the equivalent series resistance, is the resistance of the capacitor itself. If the ESR becomes high, the high frequency characteristics of the capacitor deteriorate.
To eliminate the problems in the preceding application, the present assignee studied a method for formation of a solid electrolyte layer using a powder of an organic semiconductor such as TCNQ. This method will be explained with reference to FIGS. 1A to 1H. This method, however, has not been published up to now and is first disclosed in this application.
First, as shown in FIG. 1A, a pad 102 of a substrate 100 formed with an interconnect pattern is formed with a bottom electrode 104 by sputtering or electrodeposition of Al or Ta. The pad 102 is a part of the interconnect pattern on the substrate 100 formed wider.
Next, as shown in FIG. 1B, the top surface of the bottom electrode 104 is formed with a resist layer 106 as a mask for defining a dielectric layer formation region.
Next, as shown in FIG. 1C, the top surface of the bottom electrode 104 is anodically oxidized to form a dielectric layer (Al2O3 or Ta2O5) 108.
Next, as shown in FIG. 1D, the dielectric layer 108 is supplied with powder 110′ of the TCNQ complex.
Next, a solid electrolyte layer 110 on the dielectric layer 108 and top electrode 114 on the same are formed by the following method 1 or method 2.
Method 1
The steps of FIG. 1E1 and FIG. 1F are successively performed. First, as shown in FIG. 1E1, the dielectric layer 108 is formed with a solid electrolyte layer 110 comprised of a TCNQ complex. In this case, the substrate 100 is heated by a heater 112 to heat and melt the TCNQ complex powder 110′, then the heating is stopped and the substrate is allowed to naturally cool, whereby a TCNQ complex layer (solid electrolyte layer) 110 is formed as an integral melt-solidified layer. Next, as shown in FIG. 1F, the top electrode 114 is formed by sputtering of Cu or another metal. Due to this, a capacitor comprised of the bottom electrode 104, dielectric layer 108, solid electrolyte layer 110, and top electrode 114 stacked in that order is completed.
Method 2
As shown in FIG. 1E2, a Cu or other metal foil 114 is held by suction etc. at a bonding wedge 116 and placed on the TCNQ complex powder 110′. By thermo compression bonding by the bonding wedge 116, in the same way as that shown in FIG. 1F, the TCNQ complex layer (solid electrolyte layer) 110 and the top electrode layer 114 on it are simultaneously formed. Due to this, a capacitor comprised of the bottom electrode 104, dielectric layer 108, solid electrolyte layer 110, and top electrode 114 stacked in that order is completed.
After the capacitor is completed by the above, as shown in FIG. G, the resist layer 106 is removed.
Next, as shown in FIG. 1H, an insulating layer 118 is formed to bury the capacitor by coating an insulating resin or laminating a resin film.
Finally, the insulating layer 118 is formed with vias and interconnect patterns required for a predetermined circuit and the top electrode 114 and interconnect patterns are electrically connected, whereby the circuit board is completed.
Note that in the above example, the pad 102 was shown as part of the interconnect pattern formed on the substrate 100, but the pad 102 may also be formed as part of the interconnect pattern of one layer in the multilayer interconnect structure formed on the board 100 and electrically connected with the bottom interconnect pattern.
According to the methods studied above, the problem with controllability of the position of formation and shape of formation as in the case of forming a polymer using a liquid as in the method disclosed in the preceding application does not arise. Further, the problem of the higher ESR arising due to the low electroconductivity as in the case of use of a conductive metal oxide does not arise.
However, there is a problem that when supplying powder 110′ of the TCNQ complex on the dielectric layer 108, the amount of supply of the powder becomes uneven in the plane of the dielectric layer 108.
In addition, there is the following problem in the formation of the solid electrolyte layer 110. That is, with the above method 1, when heating the substrate 100, the molten TCNQ complex is liable to flow outside of the region defined by the resist 106. On the other hand, with the above method 2, when pressing the powder 110′, mechanical damage ends up being caused to the dielectric layer 108 at the bottom.